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• Truechip Announces First Customer Shipment of UCIe Verification IP (Monday, November 28, 2022)
• Tachyum Successfully Runs LINPACK on FPGA With IEEE 754-2019 Compliant FPU (Monday, November 28, 2022)
• The MOSIS Service of the USC Information Sciences Institute and SkyWater Collaborate on Silicon IC Design Enablement and Manufacturing Service (Monday, November 28, 2022)
• QuantWare launches Foundry Services for superconducting quantum chips (Monday, November 28, 2022)
• Faraday FPGA-Go-ASIC™ Succeeds in Penetrating the Market (Monday, November 21, 2022)
• Embrace the new age of ultra-high-definition multimedia with HDMI 2.0 Rx PHY IP Cores in 12FFC process technology with matching controller (Sunday, November 20, 2022)
• Synopsys To Play A Key Role In Enabling Intel Foundry Services For US DOD Chip Program (Wednesday, November 16, 2022)
• Truechip Announces First Customer Shipment of MIPI A-PHY Verification IP (Wednesday, November 16, 2022)
• StarFive Releases StarFive StarStudio IDE, which supports both Linux and Baremetal Development (Monday, November 14, 2022)
• Marvell Announces Innovative CXL Development Platform for Multi-Host Memory Pooling (Sunday, November 13, 2022)
• JEDEC Announces Publication of the SPD5118 Hub and Serial Presence Detect Device and the DDR5 SPD Contents Specifications (Sunday, November 13, 2022)
• ZeroPoint Technologies can reduce data center energy consumption by 25% (Sunday, November 13, 2022)
• Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds (Sunday, November 13, 2022)
• ShortLink AB and Dolphin Design partner to create a highly energy-efficient Sub-GHz ASIC design platform (Thursday, November 10, 2022)
• Cryogenic CMOS design enabled by Semiwise (Thursday, November 10, 2022)
• DDR5/DDR4/LPDDR5 Combo PHY IP Cores which is Silicon Proven in 12FFC with Matching Controller IP Cores is available for license to accelerate your Memory Interfacing Speeds (Tuesday, November 8, 2022)
• Arasan announces MIPI DSI IP for FPGA supporting full C-PHY 2.0 speeds (Monday, November 7, 2022)
• Weebit Nano receives from SkyWater Technology the first silicon wafers it manufactured with embedded Weebit ReRAM (Monday, November 7, 2022)
• Chiplet Interconnect Technology Heads Toward Commercialization (Monday, November 7, 2022)
• eMemory Receives 2022 TSMC OIP Partner of the Year Award for Embedded Memory IP (Sunday, November 6, 2022)
• NSITEXE develops "DR4100" General Purpose Accelerator for SoC (Thursday, November 3, 2022)
• Silicon Creations Named 2022 TSMC OIP Partner of the Year for Analog and Mixed-Signal IP (Wednesday, November 2, 2022)
• Bitech Technologies Reports Completion of Its FPGA design and the Launch of Its ASIC Initiatives for Bitcoin Mining (Tuesday, November 1, 2022)
• Floadia Announces MTP IP without extra Mask Available on 55nm (Sunday, October 30, 2022)
• MIPI DSI and CSI Controllers IP Cores, for your High-Resolution Cameras, Display and Consumer Products, is available for immediate licensing (Sunday, October 30, 2022)
• Cadence's New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies (Wednesday, October 26, 2022)
• Cadence Integrity 3D-IC Platform Certified for TSMC 3DFabric Offerings (Wednesday, October 26, 2022)
• Weebit Nano successfully qualifies its ReRAM module (Wednesday, October 26, 2022)
• Cadence Digital and Custom/Analog Design Flows Achieve Certification for TSMC's Latest N4P and N3E Processes (Tuesday, October 25, 2022)
• Cadence Joins Intel Foundry Services USMAG Alliance to Accelerate Chip Design Development (Monday, October 24, 2022)
• Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Center and AI SoCs (Monday, October 24, 2022)
• Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0 (Monday, October 24, 2022)
• Nextera Video and Adeas ST 2110 and NMOS FPGA Cores Receive Latest JT-NM Tested Badges (Sunday, October 23, 2022)
• Marvell Announces Industry's Most Comprehensive 3nm Data Infrastructure IP Portfolio (Wednesday, October 19, 2022)
• USB-IF Announces Publication of New USB4® Specification to Enable USB 80Gbps Performance (Tuesday, October 18, 2022)
• SmartDV Achieves ISO 9001:2015 Certification (Tuesday, October 18, 2022)
• Arasan Partners with Testmetrix on its 4.5 GSPS C-PHY / D-PHY HDK and Compliance Test Platform (Monday, October 17, 2022)
• EnSilica looks to acquisitions, expands Bristol design centre (Monday, October 17, 2022)
• MOSCHIP joins TSMC Design Center Alliance (Sunday, October 16, 2022)
• eInfochips Partners with Taoglas to Offer RF Design Services to Add Wireless Connectivity to Products (Sunday, October 16, 2022)
• Brite Semiconductor Provides MIPI IP Total Solution (Thursday, October 13, 2022)
• proteanTecs Edge™ Applications Now Available on the Advantest ACS Solution Store (Wednesday, October 12, 2022)
• Weebit Nano advances its ReRAM selector development to fit embedded & discrete applications (Wednesday, October 12, 2022)
• Cadence and Google Cloud Collaborate to Advance the Electronic System and Semiconductor Design Ecosystem (Tuesday, October 11, 2022)
• New Cadence Certus Delivers Up to 10X Faster Concurrent Full-Chip Optimization and Signoff (Tuesday, October 11, 2022)
• SEMI ESD Alliance Adds Axiomise to Member Roster (Monday, October 10, 2022)
• DCD-SEMI introduces multiprotocol combo: HDLC, UART, SPI... with bigger FIFO and... (Monday, October 10, 2022)
• Introducing PCIe 4.0 PHY IP Cores in 7nm for a reliable, Low area and High-Speed Interface Peripheral slot for all your High-End Devices (Sunday, October 9, 2022)
• Synopsys Unveils Breakthrough Golden Signoff ECO Solution, Delivering 10x Productivity Improvement (Tuesday, October 4, 2022)
• Perforce Delivers Enhanced Support for Test Automation in Latest Helix ALM Release (Tuesday, October 4, 2022)