D&R News Alert
April 28th, 2025
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Welcome to the issue of April 28th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Secure-IC
EU Cyber Resilience Act (CRA) How to achieve full compliance
  • Security by design with CRA-compliant IPs & lifecycle management tools
  • Securyzr™ Server & PSIRT: vulnerability monitoring and incident response
  • Configurable EAL level, from 2 to 5+ (according to EUCC)
  • Supports SESIP-based evaluations for connected devices
>> MORE ABOUT EU-CRA >> SECURE-IC’S SOLUTIONS

Foundry Ecosystem News
■ Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
■ Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
Design Platform
■ Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge
■ Automating Hardware-Software Consistency in Complex SoCs - By Arteris
Silicon Library DisplayPort v1.4a IPs with MST support
• Fully support MST with dedicated PHY and Controller IPs
• HDCP1.4/2.3 can be added to controller
• FEC/DSC can be added to Controller
Learn more >>

Security
■ Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices
■ EU Bolsters Cybersecurity With NIS2 Directive
RISC-V
■ FPGA prototyping harnessed for RISC-V processor cores
■ Baya Systems, Imagination Technologies and Andes Technology to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley
Audio/Video IP
■ Xylon Introduces Xylon ISP Studio
Products
 ❖ XYLON ISP Studio

Automotive
■ BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
Artificial Intelligence
■ Has AI Finally Destroyed the Need for Software Testing?
Green Electronics
■ GlobalFoundries Accelerates GHG Reductions Commitments with Near Term Science-Based Target
Partner News
■ Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®
■ Aion Silicon to Showcase Advanced SoC Design Capabilities at Andes RISC-V CON Silicon Valley
■ QuickLogic to Present and Exhibit at Andes RISC-V CON Technology Summit in San Jose
■ Premier ASIC and SoC Design Partner Rebrands as Aion Silicon
Business News
■ €6m for free space photonic networks for smart factories
■ Intel’s CEO Lip-Bu Tan Reportedly Met With TSMC’s CEO To Discuss Foundry Partnership; Raising Possibility of a Deal





D&R PARTNER SPOTLIGHT

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  • Latest IP solutions such as MIPI D-PHY, C-PHY, and M-PHY
  • Silicon-proven in 12 different nodes
  • Silicon-proven in 9 different foundries
  • Supports CSI-2, DSI-2, and UniPro/JEDEC UFS
Visit mixel.com for more information


DDR5 PHY IP for TSMC N3P
• Low latency, small area, low power
• Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps

New IP
• DDR5 PHY IP for TSMC N3P by Synopsys
• 13-bit, 80 MSPS Analog-to-Digital Converter IP Block by Alphacore
• MIPI CSI-2 by Chip Interfaces
• DVB-S2X Wideband LDPC BCH Encoder IP Core by Global IP Core Sales
• Register File with low power retention mode and 3 speed options by Nordic Semiconductor

What they said at
IP SoC EU 24

Security Verification in SoCs
Ali Hmedat, Senior Design vérification Engineer, AEDVICES CONSULTING

6R Greenness Profiling for IC and Boards
Gabrièle Saucier, CEO, Design And Reuse

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