D&R News Alert
April 24th, 2025
$var->USER_FIRSTNAME

Welcome to the issue of April 24th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Do not miss IP-SoC
Silicon Valley 2025
When: April 24th, 2025 		Now Open! >>

Foundry Ecosystem
■ TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
■ Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
■ M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
■ Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC's A16 and N2P Process Technologies
■ Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
■ MosChip® to showcase Silicon Engineering Services at TSMC 2025 North America Technology Symposium
■ Thalia joins GlobalFoundries' GlobalSolutions Ecosystem to advance IP reuse and design migration
AMBA AXI4/AXI3 & AHB Multi-Channel DMA Controllers
Digital Blocks
• Configurable Number of DMA Multi-Channels
• Scatter-Gather, Linked-list Descriptor
• High Throughput on both small and large data sets
• Options for high-performance AXI4-Stream transfers

Learn more...

Analog IP
■ DVB-S2X Wideband LDPC/ BCH Encoder FEC IP Core Available For Licensing and Integration From Global IP Core
Design
■ Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows – by Synopsys
■ How NoC architecture solves MCU design challenges – by Arteris
LogicBRICKS Xylon ISP Studio PC Application

• Use GUI to build ISP for AMD FPGA and SoC
• Evaluate and tune parallel ISP pipelines in minutes
• Bit-accurate, no need for hardware retesting
• Supports Xylon logicBRICKS HDR ISP IP cores

Learn more >>

RISC-V
■ Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
■ BrainChip Extends RISC-V Reach with Andes Technology Integration
Security
■ PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography
■ Crypto Quantique publishes independent cetome analysis on streamlining CRA compliance with the QuarkLink security platform
Large Portfolio of Silicon Proven IP’s in 3n, 4/5n and 6/7n FinFets
Analog Bits
 • N3 IP’s Silicon Proven in Test Chips and Customer
   Products
• N2 Test Chips Taped-Out
Check our CEO Interview with SemiWiki >>

Artificial Intelligence
■ Alphawave Semi Delivers Foundational AI Platform IP for Scale-Up and Scale-Out Networks
■ Ceva Neural Processing Unit IP for Edge AI Selected by Nextchip for Next-Generation ADAS Solutions
■ Cadence Advances AI in the Cloud with Industry-First DDR5 12.8Gbps MRDIMM Gen2 Memory IP System Solution
■ HBM4 Boosts Memory Performance for AI Training – by Cadence
Partner News
■ Alphawave Semi Audited Results for the Year Ended 31 December 2024
Business News
■ Shifting Sands in Silicon by Global Supply Chains





New IP
• Register File with low power retention mode and 3 speed options by Nordic Semiconductor Seattle
• MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP (8.0Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC by Mixel
• PCIe 5.0 PHY IP for TSMC N5 by Synopsys
• 5V Library for Generic I/O and ESD Applications TSMC 12nm FFC/FFC+ process by Certus Semiconductor
• 8Kx8 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic/BCD Process by Attopsemi Technology

What they said at
IP SoC EU 24

How to Enhance Energy Efficiency and Reduce Costs with Advanced In-Situ Sensors?
Vincent Telandro, Product Marketing Manager, Dolphin Semiconductor

Niche gets super niche in the SEMI conductor Equipment domain
P SRINIVASA RAGHAVAN, Practice Head, Semiconductor BU, HCL TECH

Protecting Automotive Networks with MACsec Security
Bart Stevens, Senior Director of Product Marketing, Rambus, Inc.

Secure-IC Differential Loop PUF : Overcoming some weaknesses of the traditional Loop PUF while enhancing its usability
Brice GAIGNOUX, Pre-Sales Engineer EMEA, Secure-IC

The CHERI Alliance - getting security embedded into electronic systems
Mike Eftimakis, Founding Director, CHERI Alliance

REGISTER:
If this newsletter was forwarded to you by a colleague, you can have it sent directly to you at no cost. To register for D&R SoC News Alert, go to: https://www.design-reuse.com/users/signup.php

UPDATE YOUR PROFILE / UNSUBSCRIBE :
You are subscribed as $var->USER_MAIL and you receive this Alert in html format.

* If you wish to unsubscribe, you can do it there:
https://www.design-reuse.com/users/alert.php?u=$var->USER_ID&e=$var->USER_MAIL