D&R News Alert
March 10th, 2025
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Welcome to the issue of March 10th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Mixel has the most comprehensive MIPI portfolio and widest adoption in the industry
  • Latest IP solutions such as MIPI D-PHY, C-PHY, and M-PHY
  • Silicon-proven in 12 different nodes
  • Silicon-proven in 9 different foundries
  • Supports CSI-2, DSI-2, and UniPro/JEDEC UFS
Visit mixel.com for more information

Foundry News
■ Intel Foundry’s Moment of Truth: Will 18A Deliver?
■ TSMC Intends to Expand Its Investment in the United States to US$165 Billion to Power the Future of AI
Design Platform
■ Renesas and Altium Announce Introduction of Renesas 365, Powered by Altium: Groundbreaking Industry Solution for Software-Defined Products
■ Pragmatic launches platform for mixed-signal flexible ASIC design
■ Arm Compute Platform at the Heart of Malaysia’s Silicon Vision
RISC-V
■ Infineon brings RISC-V to the automotive industry and is first to announce an automotive RISC-V microcontroller family
■ Infineon, Synopsys to show virtual prototype of first automotive RISC-V microcontroller
■ €240m DARE project for AI RISC-V chiplets
Internet of Things
■ Nordic Semiconductor partners with Skylo for IoT expansion
Artificial Intelligence
■ Baya Systems Revolutionizes AI Scale-Up and Scale-Out with NeuraScale™ Fabric
■ Neurons cast in silicon: AI chip SENNA accelerates spiking neural networks
■ Europe takes a major step towards digital autonomy in supercomputing and AI with the launch of DARE project
■ From AI to satellite: Mobile World Congress 2025
Space IP
■ EnSilica Secures €2.13 Million European Space Agency Development Contract
Partner News
■ Veriest Strengthens its Software Domain Activities at embedded world 2025
■ Axelera AI Secures up to €61.6 Million Grant to Develop Scalable AI Chiplet for High-Performance Computing
■ Weebit Nano - 1H FY25 financial results
Business News
■ STMicroelectronics to ramp new silicon photonics process
■ Vietnam approves $500 million for semiconductor plant






MIPI C-PHY v2.0 D-PHY v2.1 RX for GF 12LP+
• Compliant with the latest MIPI C-PHY and D-PHY specifications
• Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry

New IP
• GDDR7 Memory PHY for TSMC N3P by Cadence Design Systems
• Ultra low-power crystal-based 32 kHz oscillator designed in TSMC 12FFC+ by Dolphin Semiconductor
• Clock Attack Monitor TSMC by Agile Analog
• Smart Network-on-Chip (NoC) IP by Arteris

What they said at
IP SoC EU 24

Secure-IC Differential Loop PUF : Overcoming some weaknesses of the traditional Loop PUF while enhancing its usability
Brice GAIGNOUX, Pre-Sales Engineer EMEA, Secure-IC

The CHERI Alliance - getting security embedded into electronic systems
Mike Eftimakis, Founding Director, CHERI Alliance

Security Verification in SoCs
Ali Hmedat, Senior Design vérification Engineer, AEDVICES CONSULTING

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