D&R News Alert
April 21st, 2025
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Welcome to the issue of April 21st, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

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Foundry News
■ Samsung achieves 40%+ test yields with 4nm logic die
Foundry Ecosystem News
■ Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium
Andes Andes 2025 RISC-V CON Silicon Valley Event

Explore Two Parallel Conference Tracks:
• Main Conference (Open to all) - Speakers, Exhibits, Networking
• Developer Track (Limited Seating) - Hands on Deep Dives
When: April 29th, 9am-5pm PDT
Where: DoubleTree by Hilton Hotel in San Jose
Learn more >>

Design Platform
■ Automating Hardware-Software Consistency in Complex SoCs
Memory Standards
■ JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
True Circuits

Why settle for old DDR technology when doing chips at older nodes? TCI offers a production proven TSMC 40G LPDDR5-3200 hard PHY configured to your exact floorplan.

TSMC 40nm G 3200Mbps LPDDR5 PHY >>
Learn more >>

RISC-V
■ New Breakthroughs in China’s RISC-V Chip Industry
■ Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
Networking
■ Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Trusted Global Leaders in Interface Semiconductor IP
• MIPI DSI-2 & DisplayPort 1.4 Semiconductor IP
• Silicon-proven to 5nm TSMC, GF, Samsung, SMIC
• Customizable PHY & Controller IP
• Hot IP: 1G Ethernet, HDMI, USB

Artificial Intelligence
■ BrainChip Gives the Edge to Search and Rescue Operations
Quantum Computing
■ Equal1 Validates CMOS-Compatible Silicon Spin Qubit Platform Using GlobalFoundries’ 22FDX Process
What’s new in FD-SOI?
Green Electronics
■ How the EU is bringing together electronics firms to combat e-waste
Partner News
■ BOS Joins Plug and Play NeoCity 2025
Business News
■ Korea unveils massive $23.2B semiconductor support plan
■ ASML targeted in latest round of US tariffs
■ Design IP Market Increased by All-time-high: 20% in 2024!
Do not miss IP-SoC
Silicon Valley 2025
Opens on April 24th, 2025 		Last Chance
to Register >>








PCIe 5.0 PHY IP for TSMC N5
• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

New IP
• Register File with low power retention mode and 3 speed options by Nordic Semiconductor Seattle
• MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP (8.0Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC by Mixel
• 5V Library for Generic I/O and ESD Applications TSMC 12nm FFC/FFC+ process by Certus Semiconductor
• 8Kx8 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic/BCD Process by Attopsemi Technology

What they said at
IP SoC EU 24

Wireless and Batteryless Interface for IoT
Polina Proskurova, Project Manager, NTLab

How to select the best Audio codec architecture to enhance your wearables?
Etienne Faucher, Product Marketing Manager, Dolphin Semiconductor

Porting ASIC IP Cores to FPGA: It's Not a Cakewalk!
Philipp Jacobsohn, Principal Application Engineer, SmartDV Technologies

Integrated Security Solutions: How SRAM-based PUF Augments Embedded Hardware Secure Modules in a Post-Quantum World
Erik van der Sluis, Principal R&D Engineer, Synopsys, Inc.

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