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New Products

Rambus, Inc.
HBM4E Memory Controller
Synopsys, Inc.
Synopsys Memory, Logic, IO for TSMC N7
Nuclei System Technology
High-Performance Processor
ARKCHIPS
TSMC UBC (Universal Bias Controller) - Power Management Unit
Mobiveil Inc.
Gen6-AglxTM

Blogs

The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs
Key ASIC
Key ASIC
ISE 2026 Recap: IntoPIX Showcases IPMX, JPEG XS, 8K And AI-Powered Workflows
intoPIX
intoPIX
ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
Quadric
Quadric
Chiplet innovation isn’t waiting for perfect standards
Arteris
Andy Nightingale
Arteris
Powering the AI Supercycle: Design for AI and AI for Design
Cadence Design Systems, Inc.
Reela Samuel
Cadence Design Systems, Inc.
Advancing High‑Performance Silicon Photonics and Silicon Germanium (SiGe) for the Next Era of Optical Connectivity
Radhika Arora
GlobalFoundries
Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
Synopsys, Inc.
LJ Chen
Synopsys, Inc.
Flexible Ethernet IP Licensing for Secure, Scalable Silicon Development
Comcores
Comcores
Transforming the Automotive Experience with Cadence Tensilica DSPs
Cadence Design Systems, Inc.
SriramK
Cadence Design Systems, Inc.
Accelerating Multi-Die Innovation: How Synopsys and Samsung are Shaping Chip Design
Synopsys, Inc.
Amlendu Shekhar Choubey
Synopsys, Inc.
Accelerating Chiplet Innovation with a New Partner Ecosystem
Cadence Design Systems, Inc.
Mick Posner
Cadence Design Systems, Inc.
From Fab to the Field: Accelerating Trusted U.S. Semiconductor Onshoring for Mission-Critical Defense
GlobalFoundries

Articles

Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight
Francisca Tan, Senior Product Manager, Tessent Embedded Analytics
Siemens Digital Industries Software
Securing UALink: Introducing Synopsys UALinkSec_200 Security Module
Synopsys, Inc.
Dana Neustadter, Vincent van der Leest
Synopsys, Inc.
Creating a Frequency Plan for a System using a PLL
Perceptia Devices
Julian Jenkins
Perceptia Devices
PUF-PQC Integrated with PUFrt to Solve PPA Challenge for SoCs
eMemory Technology Inc.
eMemory & PUFsecurity
eMemory Technology Inc.
From Silos to Systems, from Data to Insight
Keysight Technologies
Keysight Technologies
Security certification and the crucial role of anti-tamper sensor solutions
Agile Analog
Chris Morrison
Agile Analog
Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight
Siemens EDA
Francisca Tan, Senior Product Manager
Siemens EDA
Three Ethernet Design Challenges in Industrial Automation
Key ASIC
Key ASIC
ST silicon photonics and BiCMOS technologies: the winning portfolio for AI optical interconnects
STMicroelectronics
STMicroelectronics
AI in VLSI Physical Design: Opportunities and Challenges
Japesh Kumar, Qualcomm
AI-Driven and Traditional Approaches to Accident Scenario Reconstruction
Vayavya Labs
Nitin Swamy
Vayavya Labs
From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security
PQSecure Technologies
PQSecure Technologies
Asic Technology
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FPGA and eFPGA Corner
Select your target vendor and device
Today on Design And Reuse

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bullet_arrow  Cadence and NVIDIA Unveil Accelerated Engineering Solutions Purpose-Built for Agentic AI Chip and System Design​ - March 26, 2026

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