Design Platform News
-
HCLTech Forges Ahead in Engineering Services to global Communication Services Providers (CSPs) with purchase of Communications Technology Group assets from Hewlett Packard Enterprise (HPE)
(Wednesday, May 22, 2024)
-
S2C and Sirius Wireless Collaborate on Wi-Fi 7 RF IP Verification System
(Tuesday, May 21, 2024)
-
JEDEC Reveals Massive Speed Boosts For Next-Gen DDR6 And LPDDR6 Memory
(Tuesday, May 21, 2024)
-
Analog Bits Joins the Silicon Catalyst In-Kind Partner Ecosystem
(Tuesday, May 21, 2024)
-
Why verification matters in network-on-chip (NoC) design
(Monday, May 20, 2024)
-
JEDEC Confirms CAMM2 Memory For Desktop PCs: DDR6 Up To 17.6 Gbps & LPDDR6 Up To 14.4 Gbps
(Monday, May 20, 2024)
-
Crucial role for imec in EU Chips Act
(Monday, May 20, 2024)
-
Qualitas Semiconductor expands presence in chinese market through strategic partnership with chinese chip design company
(Sunday, May 19, 2024)
-
Defacto SoC Compiler performance on AWS Graviton3
(Thursday, May 16, 2024)
-
ADTechnology and ANAFLASH to Team Up for Embedded Vision Summit (EVS) showcase
(Monday, May 13, 2024)
-
Silicon Proven PCIe 5.0 PHY and Controller IP Cores in 12nm to Revolutionize Connectivity solutions
(Sunday, May 12, 2024)
-
NEO Semiconductor Reveals a Performance Boosting Floating Body Cell Mechanism for 3D X-DRAM during IEEE IMW 2024
(Sunday, May 12, 2024)
-
Demonstrating the UCIe Chiplet Interconnect
(Sunday, May 12, 2024)
-
TSMC Certifies a Host of Top EDA Tools for New Process Nodes
(Tuesday, May 7, 2024)
-
Siemens delivers end-to-end silicon quality assurance for next-generation IC designs with new Solido IP Validation Suite
(Monday, May 6, 2024)
-
Announcing Availability of Silicon-Proven 12bit 1Msps SAR ADC IP Core for Whitebox Licensing with Royalty Free
(Sunday, May 5, 2024)
-
Fabless semiconductor startup Mindgrove launches India's first indigenously designed commercial high-performance MCU chip
(Sunday, May 5, 2024)
-
Zhuhai Chuangfeixin: OTP IP Based on 55nm High-Voltage Process Successfully Qualified for Listing
(Sunday, May 5, 2024)
-
PCI-SIG® Announces CopprLink™ Cable Specifications for PCIe® 5.0 and 6.0 Technology
(Wednesday, May 1, 2024)
-
Intel aims to produce scalable silicon-based quantum processors
(Wednesday, May 1, 2024)
-
Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)
(Tuesday, April 30, 2024)
-
EDA toolset parade at TSMC's U.S. design symposium
(Sunday, April 28, 2024)
-
Rambus Expands Chipset for Advanced Data Center Memory Modules with DDR5 Server PMICs
(Sunday, April 28, 2024)
-
Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
(Thursday, April 25, 2024)
-
Numem at the Design & Reuse IP SoC Silicon Valley 2024
(Wednesday, April 24, 2024)
-
Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
(Tuesday, April 23, 2024)
-
Credo at TSMC 2024 North America Technology Symposium
(Tuesday, April 23, 2024)
-
Leveraging Cryogenics and Photonics for Quantum Computing
(Tuesday, April 23, 2024)
-
RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
(Monday, April 22, 2024)
-
Fundamental inventions enable the best ppa and most portable eFPGA/DSP/SDR/AI IP for adaptable SOCs
(Monday, April 22, 2024)
-
T2M-IP Unveils Revolutionary MIPI D-PHY & DSI Controller IP Cores with speed 2.5Gbps/lane, Redefining High-Speed Data Transfer and Display Interfaces
(Sunday, April 21, 2024)
-
Palladium emulation: Nvidia's Jensen Huang is a fan
(Sunday, April 21, 2024)
-
Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
(Thursday, April 18, 2024)
-
TSMC Reports First Quarter EPS of NT$8.70
(Thursday, April 18, 2024)
-
Demonstration of Weebit ReRAM on GF 22FDX® Wafers at EW24
(Wednesday, April 17, 2024)
-
Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
(Wednesday, April 17, 2024)
-
Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
(Wednesday, April 17, 2024)
-
Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
(Wednesday, April 17, 2024)
-
Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass-Produced
(Tuesday, April 16, 2024)
-
JEDEC Updates JESD79-5C DDR5 SDRAM Standard: Elevating Performance and Security for Next-Gen Technologies
(Tuesday, April 16, 2024)
-
Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
(Tuesday, April 16, 2024)
-
Movellus Extends Droop Management Leadership with Aeonic Generate™ AWM3
(Monday, April 15, 2024)
-
Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
(Sunday, April 14, 2024)
-
Khronos Releases OpenXR 1.1 to Further Streamline Cross-Platform XR Development
(Sunday, April 14, 2024)
-
Siemens and Microsoft to converge Digital Twin Definition Language with W3C Thing Description Standard
(Sunday, April 14, 2024)
-
Creonic GmbH Introduces Fast Fourier Transform IP Core
(Thursday, April 11, 2024)
-
Logic Fruit Technologies Inc. Excitedly Welcomes Mr. Akshaya Sharma as the new CEO of US Operations
(Thursday, April 11, 2024)
-
AI-Driven HBM Uptake Is Power-Sensitive
(Monday, April 8, 2024)
-
Silicon-Proven 12-Bit 5Msps ADC IP Core for High-Speed Data Conversion, Now Available for Licensing
(Sunday, April 7, 2024)
-
sureCore announces low power memory compiler for 16nm FinFET
(Wednesday, April 3, 2024)