Design Platform News
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GUC Tapes Out AI/HPC/Networking Platform on TSMC CoWoS Technology
(Tuesday, June 22, 2021)
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Alphawave IP Adopts Diakopto's ParagonX EDA Platform and Methodology
(Monday, June 21, 2021)
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Imec demoes integrated forksheet FETs for 2nm processes
(Wednesday, June 16, 2021)
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CEA-Leti Collaborates with Siemens to Launch Process Design Kit that Supports Multiple Technologies, Simplifies Creation of Optical Circuits
(Wednesday, June 16, 2021)
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Thalia Design Automation partners with Sofics to enhance offering for analog circuit and IP reuse
(Tuesday, June 15, 2021)
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Siemens Enhances Nucleus ReadyStart for Arm Platforms
(Wednesday, June 9, 2021)
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New Cadence Allegro X Design Platform Revolutionizes System Design
(Tuesday, June 8, 2021)
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Siemens acquires proFPGA product family from PRO DESIGN to expand industry-leading IC verification portfolio
(Monday, June 7, 2021)
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Siemens EDA Tools Now Qualified on TSMC's N3, N4 Processes
(Sunday, June 6, 2021)
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Aldec Launches HES-DVM Proto "Cloud Edition" - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping
(Tuesday, June 1, 2021)
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TSMC Technology Symposium: Siemens verification for TSMC 4nm and 3nm
(Tuesday, June 1, 2021)
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Cadence Unleashes Clarity 3D Solver on the Cloud for Straightforward, Secure and Scalable Electromagnetic Analysis of Complex Systems on AWS
(Tuesday, May 25, 2021)
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Imperas Simulation Reference Models selected by IAR Systems for Arm 64bit
(Tuesday, May 25, 2021)
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PLDA Announces XpressRICH PCI Express 6.0 Controller IP for Next Generation SoC Designs
(Monday, May 24, 2021)
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Avery Design Launches PCI Express 6.0 Verification IP to Enable Early Development, Compliance Checking for New Version of Standard
(Monday, May 24, 2021)
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Thalia's AMALIA Technology Analyzer de-risks Analog IP reuse for major IP houses and IC manufacturers
(Monday, May 17, 2021)
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Synopsys unveils breakthrough in emulation performance
(Monday, May 17, 2021)
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Sondrel's latest reference IP platform enables ultra-powerful signal and data processing SoCs to be created faster for lower costs
(Sunday, May 9, 2021)
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Synopsys Delivers Enhanced Memory Design Productivity to Nanya Technology
(Tuesday, May 4, 2021)
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SmartDV Unveils Automation Tool Suite for Use with Its Extensive Verification IP Portfolio
(Monday, May 3, 2021)
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Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications
(Tuesday, April 27, 2021)
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"KI-PREDICT" – Intelligent process monitoring with on-sensor signal preprocessing
(Tuesday, April 27, 2021)
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Cadence collaborates with Arm to accelerate SoC development
(Tuesday, April 27, 2021)
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Siemens Place-and-route Solution Now Qualified on TSMC's N6 Technology
(Thursday, April 22, 2021)
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proteanTecs Joins Open Compute Project, Unveils UCT Monitoring System
(Thursday, April 22, 2021)
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Synopsys Introduces PrimeLib Unified Library Characterization and Validation Solution for Accelerated Access to Advanced Process Nodes
(Tuesday, April 20, 2021)
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Hardent Selected as Design Services Provider for New Xilinx Kria SOMs
(Tuesday, April 20, 2021)
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Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs
(Monday, April 19, 2021)
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Synopsys Unleashes PrimeSim Continuum Solution to Accelerate the Design of Hyper-Convergent ICs for Memory, AI, Automotive and 5G Applications
(Monday, April 19, 2021)
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Avery Design Debuts CXL 2.0 System-level VIP Simulation Solution
(Wednesday, April 14, 2021)
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Semiconductor Energy Laboratory and Silvaco Jointly Develop SPICE Model of Oxide Semiconductor FETs
(Tuesday, April 13, 2021)
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UK memory startup raises €1.5m, looks to imec
(Tuesday, April 6, 2021)
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Siemens Emulation and Prototyping Tools Tackle SoC Design Challenges
(Saturday, April 3, 2021)
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Truechip Adds New Customer Shipments Of Verification IPs For DDR, LPDDR And I3C v1.1
(Wednesday, March 31, 2021)
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Cadence Unveils Next-Generation Sigrity X for Up to 10X Faster System Analysis
(Tuesday, March 16, 2021)
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Vtool Appoints EmergeTek as Cogita Sales Representative
(Wednesday, March 10, 2021)
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Thalia successfully completes 20th 22nm analog IP reuse engagement
(Wednesday, March 3, 2021)
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Synopsys Announces Euclide to Accelerate Design and Verification Productivity
(Tuesday, March 2, 2021)
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Achronix and Mobiveil Announce Partnership to Deliver High-Speed Controller IP and FPGA Engineering Services
(Tuesday, March 2, 2021)
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Synopsys Delivers Breakthrough Performance with New ZeBu Empower Emulation System for Hardware-Software Power Verification
(Tuesday, February 23, 2021)
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Synopsys Receives Customers' Choice Award for Paper Presented at TSMC 2020 Open Innovation Platform Ecosystem Forum
(Monday, February 8, 2021)
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Pulsic Delivers Real-Time, Accurate, Layout Previews to Analog Circuits Designers with the new Animate Preview
(Wednesday, February 3, 2021)
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Mirabilis Design integrates Fast Functional Processors into VisualSim Architect to close the software design, development and validation loop
(Tuesday, January 26, 2021)
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HDL Design House Partners with Marketing Platform AnySilicon
(Tuesday, January 26, 2021)
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Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements
(Tuesday, January 19, 2021)
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Sondrel Selects Synopsys Fusion Design and Verification Platforms to Displace Legacy Design Tools
(Monday, January 18, 2021)
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Sofics and Hardent join Mixel's MIPI ecosystem to provide designers a complete MIPI solution
(Tuesday, December 15, 2020)
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UVM Reference Implementation Aligned with IEEE 1800.2-2020 Standard
(Tuesday, December 15, 2020)
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The DDR5 Revolution: Promise & Challenges Ahead
(Thursday, December 10, 2020)
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Renesas Strengthens IP License Portfolio with IP Utilities to Facilitate Device Development
(Wednesday, December 9, 2020)
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