Synopsys' HAV systems aim to boost chip design speed and quality.
www.eetasia.com, Apr. 01, 2025 –
Synopsys recently launched two new hardware-assisted verification (HAV) systems, intended to address the need for specialized hardware to manage the complexity of modern chip design. In this article, we look at the rationale for HAV and look into the two new systems.
The rationale for HAV hardware
In a recent interview, Frank Schirrmeister, executive director of strategic programs at Synopsys, provides some insights into large-scale chip and chiplet designs.
Designing AI accelerator chips is an exceptionally complex endeavor. Modern chips integrate billions of transistors and diverse processing units (CPUs, NPUs, GPUs, etc.), all working in parallel. Verifying such complexity with traditional simulation is daunting—it is not just for functional correctness but also for ensuring power efficiency and performance targets are met under real workloads.
New AI accelerators typically employ workload-specific optimizations (e.g. low-precision arithmetic, novel dataflows) that demand extensive architectural validation. The sheer scale of operations (often quadrillions of cycles for complete verification makes software simulation alone infeasible).
Moreover, these chips run sophisticated software stacks (drivers, AI frameworks), so hardware verification now must include early software bring-up and co-validation. Finally, high-speed memory and I/O interfaces (HBM, PCIe, etc.) add another layer of complexity and must be validated at real-world speeds to avoid bottlenecks. In short, AI accelerators push verification beyond the limits of traditional methods in terms of scale, speed and scope.
Adopting HAV systems yields several tangible benefits for advanced chips in general and AI accelerator projects in particular:
Faster verification cycles: hardware-assisted emulation and prototyping can speed up verification throughput by orders of magnitude. Tests that take days or weeks in traditional software simulation can run on an FPGA-based emulatorin mere hours. HAV enables teams to run more scenarios and regressions, increasing confidence in the design.
Early software bring-up and validation: software teams must develop and test firmware, drivers and AI models long before the silicon is available. With HAV, developers can boot an operating system on the emulated accelerator or use an FPGA prototype to run real AI workloads against the design. This early software/hardware co-validation means that by the time the silicon arrives, both hardware and software have been validated together, reducing integration issues. Concurrent software and silicon development engineered in parallel can significantly speed up time to market and design confidence.
Higher verification coverage and accuracy: HAV enables running a much larger number of cycles and more complex scenarios than traditional simulation. Engineers can test more corner-case scenarios, long-running sequences and complete application workloads to uncover bugs that short simulations might miss. The result is a more thoroughly validated design with fewer hidden bugs, directly reducing the risk of catastrophic silicon failures. In addition, emulators are cycle-accurate at the RTL level, so the behavior closely matches actual silicon, increasing the accuracy of verification results.
Identification of performance bottlenecks: an AI accelerator’s actual throughput can only be assessed by running near real-time workloads on prototypes. This feedback can lead to design tweaks (e.g. adjusting buffer sizes or scheduling algorithms) before tape-out. Likewise, power usage can be monitored so the team can ensure the chip meets its power efficiency goals.
Reduced risk of silicon re-spins: risk mitigation is arguably the most significant benefit of HAV. Hardware-assisted solutions considerably reduce the likelihood of uncovering a critical bug in silicon by identifying functional bugs, integration issues or performance problems during pre-silicon verification. Avoiding a silicon re-spin (a redesign and tape-out) can save millions of dollars and several months. Companies that extensively utilize HAV report fewer post-silicon surprises, ensuring more robust designs.
Shorter time-to-market: these factors—faster verification, concurrent software development and avoiding rework—combine to shorten the overall development cycle. A well-verified chip can confidently go into manufacturing, and software can be ready to deploy on real hardware when the chip returns from the fab, giving companies a competitive edge in the fast-moving AI market.
Synopsys’ expanded HAV portfolio
According to Synopsys, the new Synopsys HAPS-200 prototyping and ZeBu-200 emulation systems provide fast performance. They use the latest AMD Versal Premium VP1902 adaptive SoC, which expands functionality over a traditional FPGA.
HAPS is designed primarily for FPGA-based prototyping. It is used for early software bring-up, system-level validation and real-world integration testing. HAPS’ performance claims to be near real-time speed (i.e. GHz), enabling teams to validate early operating system and real-world application testing.
ZeBu is Synopsys’ hardware emulator, designed to verify digital designs with cycle accuracy. It validates the detailed functional behavior of a chip’s RTL before tape-out. Design teams typically utilize both prototyping and emulation, beginning with software at the system level and then transitioning to emulation at the RTL level for verification and debugging.
The HAPS-200 and ZeBu-200 systems use the Synopsys EP-Ready hardware platform to eliminate the necessity of pre-determining the appropriate balance between emulation and prototyping hardware. This hardware platform allows for the reconfiguration of cables and hubs, providing direct and scalable connectivity, and it accommodates configuration for emulation and prototyping use cases across multiple projects on a single hardware platform.
In addition, enhanced modular HAV methodology scales ZeBu Server 5 to complex designs of over 60 billion gates. The company said its hybrid technology utilizing Synopsys Virtualizer virtual prototypes now supports multi-threading and delivers Android boot in less than 10 minutes.
While extending design capacity to 15.4 billion gates, the ZeBu-200 emulation system offers up to 2× higher runtime performance than the previous generation ZeBu EP2 with faster compile time, reducing turnaround time and enhancing development productivity. It features up to 8× better debug bandwidth, offering 200GB debug trace memory per module and improved job scheduling and relocation.
Already in use with customers leveraging HAPS prototyping, Synopsys has extended its modular HAV methodology to ZeBu Server 5. This expands its scalability beyond 60GB to meet the industry’s growing emulation capacity needs, significantly reducing compile time and compute resources and enabling emulation for the largest multi-die designs.
Early customer reactions
“With the growing market demand for managing large AI computational data sets necessitating significant GPU and CPU computational power, the development timeline for Nvidia’s next-generation AI systems has become highly compressed to an annual release cycle, requiring best-in-class prototyping solutions,” according to Nvidia’s vice president of hardware engineering, Narendra Konda. “The 50 MHz performance we have achieved with HAPS-200 has been instrumental in enhancing the productivity of our software development teams. We look forward to expanding our HAPS-200 deployment to fully leverage our software development teams.”
The bottom line
HAV has become indispensable for AI accelerator design teams. It addresses the critical challenges of verifying incredibly complex, high-performance chips under realistic conditions. By leveraging solutions like Synopsys’ HAV portfolio, it is possible for teams to achieve greater confidence in their designs, hit aggressive performance/power targets and avoid costly mistakes—all while accelerating the overall development cycle.
While dedicated emulation hardware requires a significant investment, this cost must be weighed against the potential expense of a silicon failure. The cost of a re-spin can far exceed the cost of emulation, making robust verification a worthwhile investment with a strong ROI. Moreover, the financial advantage of a faster time to market can more than offset the initial expenses. The ability to rapidly conduct “quadrillions of cycles” of verification before tape-out is a game-changer for delivering reliable silicon on schedule and within budget.