Highlights
- Achieved up to 2X improved productivity versus the previous methodology
- Experienced a 50% reduction in both design closure turnaround time and total compute and memory costs
www.cadence.com/en_US/home.html, Oct. 31, 2023 –
SAN JOSE, Calif.– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Realtek successfully used the Cadence® Tempus™ Timing Solution to sign off an N12 high-performance CPU core while achieving significantly improved power, performance and area (PPA). By adopting the Tempus Timing Solution, Realtek realized a 2X boost in productivity and reduced design closure turnaround time by 50% versus their previous methodology. In addition, Realtek reduced their compute costs and memory footprint by 50%.
Cadence signoff solutions provided the Realtek team with several key benefits, including:
- Accurate golden signoff analysis: Cadence's Tempus Timing Solution and Quantus™ Extraction Solution empowered the Realtek team to confidently deliver accurate, working silicon
- Improved productivity and reduced schedule time: The Tempus ECO Option with SmartMMMC Optimization enabled Realtek to converge timing closure faster with fewer iterations from within the Innovus™ Implementation System
- Compute resource savings: The Tempus CMMMC feature with concurrent multi-mode multi-corner technology allowed Realtek to implement all views in a single run so they could reach design closure faster while significantly conserving machine resources
"Meeting our time-to-market deadlines with optimally performing parts is crucial to our business, and the Cadence Tempus Timing Solution helped us achieve those goals," said Yee-Wei Huang, vice president at Realtek. "Thanks to our successful N12 design project collaboration with Cadence, where we rapidly achieved working silicon, we plan to deploy the Tempus Timing Solution throughout multiple new projects across a wide range of technologies."
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