Highlights:
www.cadence.com/en_US/home.html, Jun. 28, 2023 –
SAN JOSE, Calif.– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry's SF2 process node. This latest collaboration between Cadence and Samsung Foundry enables customers to leverage the Cadence® digital full flow and corresponding process design kit (PDK) to speed next-generation mobile, automotive, AI and hyperscale chip design innovation. The flow has already been validated with the completion of a successful 2nm test chip tapeout.
The complete Cadence RTL-to-GDS flow that is optimized for the Samsung Foundry 2nm process technology includes the Genus™ Synthesis Solution, Innovus™ Implementation System, Integrity™ 3D-IC platform, Quantus™ Extraction Solution, Pegasus™ Verification System, Voltus™ IC Power Integrity Solution, Tempus™ Timing Signoff Solution and Tempus ECO Option. Backside routing improves PPA results and reduces congestion on the frontside layers and can be used for power distribution networks, clock tree nets and signal routing. Accordingly, the four Innovus Implementation System engines have been optimized for the Samsung Foundry 2nm process: