101 30.0

DPA- and FIA-resistant Ultra High Bandwidth FortiCrypt AES IP core Intro The AES XP-DPA-FIA IP core belongs to the FortiCrypt product family. It is intended for applications that require the handling of ultra-high ban...

102 30.0

Secure-IC's Securyzr(TM) Network Security Crypto Accelerator To answer the needs of high-performance systems, a new generation of powerful processors is being designed and deployed. These multi-core SoCs contain...

103 30.0

Secure-IC's Securyzr(TM) SM4 Crypto Engine The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of China. It is complian...

104 30.0

Silicon Security Solution ChevinID™ was designed by Chevin Technology using patented method (GB2609026) to add a further layer of protection to your Silicon supply chain by ide...

105 30.0

Media Access Control Security (MACSec) Media Access Control Security (MACSec) is an IEEE standards-based protocol for securing communication among the trusted components of an 802.1 LAN. MA...

106 30.0

RSA-ECC High-Performance Multi Public Key Engine The High-Performance Multi Public Key Engine is a secure connection engine that can be used to offload the compute intensive Public Key operations (Di...

107 25.0

Secure-IC's Securyzr(TM) DDR Encrypter The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory. It supports AXI slave/master interfaces,...

108 25.0

Secure-IC's Securyzr(TM) DDR Encrypter The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory. It supports AXI slave/master interfaces,...

109 25.0

Secure-IC's Securyzr(TM) Blockchain Hardware Accelerator Blockchain has a wide range of applications on the internet. As it is decentralized by design, it is an alternative to the many traditional transactio...

110 25.0

PUSCH Decoder for 3GPP 5G NR 3GPP compliant coding and modulation for Physical Shared Channels The Physical Uplink Shared Channel (PUSCH) is used to for uplink data which is sh...

111 25.0

PDSCH Encoder for 3GPP 5G NR 3GPP compliant coding and modulation for Downlink Physical Shared Channels The Physical Downlink Shared Channel (PDSCH) is used for downlink data w...

112 23.0

HDCP Encryption-Decryption Engine The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption-Decryption Engine IP core allows system designers to accelerate...

113 20.0

FEC As serial link speeds have increased, the reach achievable has become more and more limited by the lossy nature of the physical media which introduces...

114 20.0

Secure-IC's Securyzr™ Chacha20-Poly1305 Multi-Booster - 800Gbps The ChaCha20-Poly1305 Multi-Booster Crypto Engine is RFC7539 compliant to provide Authenticated Encryption with Associated Data (AEAD) using the ChaCh...

115 20.0

Secure-IC's Securyzr™ Memory & Bus Protection IP Core The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI ...

116 20.0

AES-XTS encryption/decryption IP SphinX is designed to accommodate the speed, latency and throughput requirements of high performance computer systems main memory / DRAM. The IP imple...

117 20.0

High-Performance AES-GCM/CTR IP The compact, high-performance Synopsys Pipelined AES-GCM/CTR Core implements the AES-GCM/CTR algorithm as specified in the National Institute of Stand...

118 20.0

High-Performance AES-XTS/ECB IP Memory and storage security involves protecting storage resources and the data stored on them, both on-premises and in external data centers and the c...

119 20.0

Multipurpose Security Protocol Accelerator Complex system-on-chip (SoC) requirements can include security at the MAC layer, VPN layer, and application layer. The SynopsysSecurity Protocol Accel...

120 20.0

PUSCH Equalizer for 3GPP 5G NR Advanced 3GPP compliant equalisation, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel solution Acc...

121 20.0

Post-Quantum Hardware Accelerator (PQP-HW-HBS) PQPlatform-Hash (PQP-HW-HBS) is a power side-channel-secure Keccak hardware accelerator for the SHA-3 and SHAKE algorithms. It includes the PQShield-s...

122 20.0

Post-Quantum Cryptography Processing Engine (PQP-HW-LAT) PQPlatform-Lattice (PQP-HW-LAT) is a lattice engine that implements the ML-KEM and ML-DSA post-quantum algorithms. It is powered by PQShield-supplied ...

123 20.0

Post-Quantum Cryptography Processor (PQP-HW-COP) PQPlatform-CoPro (PQP-HW-COP) adds PQShield’s state-of-the-art post-quantum cryptography (PQC) to your security sub-system, with optional side-channel...

124 20.0

Post-Quantum Security Subsystem (PQ-HW-SUB) PQPlatform-SubSys (PQP-HW-SUB) is a cryptographic subsystem, designed to provide cryptographic services. These services include post-quantum signature...

125 20.0

High Capacity Post-Quantum Cryptography Processor (PQF-HW-LAT) PQPerform-Lattice (PQF-HW-LAT) is a powerful hardware-based product that is designed for high throughput and high speed. PQF-HW-LAT adds post-quantum ...

126 19.0

Hardware Security Module (HSM) The HSM IP module is a Hardware Security Module for a wide range of applications. It is developed, validated and licensed by Secure-IC (partner of Xil...

127 16.0

On-chip protection against IEC61000-4-2 events ESD solutions and Analog Pads * All voltage domains (0.85V to 5.0V) * Additional higher voltage ranges in BCD processes * High ESD levels (scal...

128 15.5556

Hardware Security Platform Our FPGA based Hardware Security Modules are offered both as IP Core and as a separate chip. The Enhanced Hardware Security Modules is extension of th...

129 15.5556

Cryptography Accelerator FPGA IP core implementation of a various cryptographic algorithms, including new, post-quantum standards, available as customizable cryptographic acce...

130 15.5556

Customizable cryptographic accelerator FPGA IP core implementation of a various cryptographic algorithms, including new, post-quantum standards, available as customizable cryptographic acce...

131 15.5556

Trusted Platform Modules Our FPGA based Trusted Platform Modules are offered both as IP Core and as a separate chip. We offer two types of TPM:Regular Trusted Platform Modules...

132 15.0

SHA-3 Secure Hash Function Core The SHA-3 is a high-throughput, area-efficient hardware accelerator for the SHA-3 cryptographic hashing functions, compliant to NIST’s FIPS 180-4 and ...

133 15.0

Advanced HMAC SHA2 DPA- and FIA-Resistant Software Library The FortiMac library belongs to the FortiMac product family. This software library provides ultra-strong protection against SCA, FIA, and cache attack...

134 12.0

AES-XTS for Storage Encrypt/Decrypt Core The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NI...

135 11.0

CC-100IP-PI Power Integrity Enhancement IP The CC-100IP-PI on Chip IP Block is an on-chip adjustable Impedance Controlled Hyper- capacitor with a Capacitance Multiplication, Series Inductance N...

136 11.0

CC-100IP-RF Analog and RF Sensitivity Enhancement IP The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series I...

137 10.0

Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks The Synopsys ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrate security into their...

138 10.0

DPA- and FIA-Resistant Balanced FortiCrypt AES IP Core Intro The AES SX-DPA-FIA IP Core is a part of the FortiCrypt product family. It provides a balanced solution with a gate count comparable to unprotect...

139 10.0

DPA and FIA-resistant Ultra-Compact FortiCrypt AES IP core Intro The AES UC-DPA-FIA IP Core belongs to the FortiCrypt product family. Like all the FortiCrypt product family members, this IP provides the highes...

140 10.0

MACsec Protocol Engine for 10/100/1000 Ethernet The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports all c...

141 10.0

Post Quantum ready Public Key Crypto HW acceleration library optimized for networking applications eSi-PQC-HT is a post quantum ready Public Key Crypto HW acceleration library, optimized for networking applications. eSi-PQC-HT supports the followi...

142 10.0

HMAC-SHA256 Accelerator Chevin Technology’s HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes. Message authe...

143 10.0

Secure Hash Algorithm-3 (SHA-3) CYB- SHA3 implements Secure Hash Algorithm-3 (SHA-3) family of functions on binary data with the NIST FIPS 202 Standard. It supports...

144 10.0

SHA256 Encoder and Decoder SHA256 is a Secure Hash Algorithms which is one of the latest hash functions standarized by the U.S Federal Government. SHA 256 IP Core Algorithm impl...

145 10.0

SHA-3 Crypto IP Core The SHA-3 – secure hash algorithms – crypto engine is a hardware accelerator for cryptographic hashing functions. It is an area efficient and high thr...

146 10.0

AES Encrypt/Decrypt 128/192/256 Low Latency, Low power, low footprint 128/192/256 bit AES Encryption / Decryption...

147 10.0

Secure-IC's Securyzr™ ChaCha20-Poly1305 Crypto Engine The ChaCha20-Poly1305 Crypto Engine is RFC7539 compliant to provide Authenticated Encryption with Associated Data (AEAD) using the ChaCha20 stream cip...

148 10.0

Secure-IC's Securyzr™ Inline Decrypter IP Core The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash. It is often used to protect the source code from decompiling o...

149 10.0

Secure-IC's Securyzr™ SHA-3 Crypto Engine The SHA-3 crypto engine has integrated flexibility and scalability to allow for high throughput and a configurable number of hashing rounds per clock ...

150 10.0

Secure-IC's Securyzr™ Deterministic Random Bit Generator (DRBG) The Deterministic Random Bit Generator is an essential silicon-proven digital IP core for all FPGA, ASIC and SoC designs that targets cryptographicall...