Getting better performance by creating a processor core with custom instructions targeted to address bottlenecks.
semiengineering.com, May. 28, 2020 –
Last month was the 55th anniversary of Gordon Moore's famous paper Cramming more components onto integrated circuits. He took a long-term view of the trends in integrated circuits being implemented using successively smaller feature sizes in silicon. Since that paper, integrated circuit developers have been relying on three of his predictions:
These predictions have largely held true for almost half a century, enabling successive generations of processors to achieve higher computational performance through greater processor complexity and higher clock speeds. These improvements were mainly delivered through general-purpose processors implemented in new technology nodes.
From about 2005, the improvements in clock frequency began to level off, leading to a leveling-off of single thread performance. Since then, using multiple cores on a single die has become commonplace, but again these cores were mainly general-purpose ones, whether application processors or MCUs.
If you are designing a chip with some performance challenges, do you simply follow Moore's law and move into a smaller silicon geometry and use general-purpose processor cores? That could be a costly approach since mask-making costs are higher in small geometries. Also, you may not achieve your performance in the most efficient way.