The ESP32-S2's main 240MHz Xtensa LX7 CPU is joined by an ultra-low-power RISC-V coprocessor built into the RTC block.
hackster.io, Mar. 02, 2020 –
Espressif has announced that its next-generation ESP32-S2 systems-on-chip (SoCs), modules, and related development boards are now in mass production – offering up to 240MHz operation and 320kB of static RAM (SRAM), along with a range of security enhancements – and, for the first time, a RISC-V coprocessor.
The latest in the ESP32-S family, which launched last year as an upgrade to the ESP32 with a focus on security and cryptography functionality, the ESP32-S2 is based on a 240MHz Xtensa 32-bit LX7 single-core processor and includes 320kB of on-board static RAM (SRAM) alongside 128kB of flash ROM. Interestingly, the part also includes an ultra-low-power coprocessor based on the free and open source RISC-V instruction set architecture.