The open-source architecture faces a long road through software standards from its beachhead as an SoC controller to use as a host processor.
SAN JOSE, Calif., Feb. 18, 2019 – Now that RISC-V has established a beachhead as a deeply embedded controller in SoCs, it's time to start asking the next question: Can this open-source instruction-set architecture (ISA) make the next big leap into being an alternative to Arm and the x86 as a host processor?
The short answer is yes, but it could take several years and there are plenty of pitfalls along the way. Essentially, the freewheeling open-source community behind RISC-V will need to develop and adhere to a wide range of system-level standards.
So far, Nvidia and Western Digital plan to use RISC-V controllers in their SoCs, and Microsemi will use it in a new FPGA. Andes, Cortus, and startup SiFive sell IP cores, and a handful of startups plan to launch mainly machine-learning accelerators using it.
RISC-V is in as many as 20 million fitness bands and smartwatches in China. In the U.S., SiFive has shipped more than 2,500 development boards using processors that it aims to sell as IP cores or as SoCs through its design services.
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