edn.com, Dec. 26, 2024 –
Alphawave Semi's Gen3 UCIe Die-to-Die (D2D) IP subsystem enables chiplet interconnect rates up to 64 Gbps. Building on the successful tapeout of its Gen2 36-Gbps UCIe IP on TSMC's 3-nm process, the Gen3 subsystem supports both high-yield, low-cost organic substrates and advanced packaging technologies.
At 64 Gbps, the Gen3 IP delivers over 20 Tbps/mm in bandwidth density with ultra-low power and latency. The configurable subsystem supports multiple protocols, including AXI-4, AXI-S, CXS, CHI, and CHI-C2C, enabling high-performance connectivity across disaggregated systems in HPC, data center, and AI applications.
The design complies with the latest UCIe specification and features a scalable architecture with advanced testability, including live per-lane health monitoring. UCIe D2D interconnects support a variety of chiplet connectivity scenarios, including low-latency, coherent links between compute chiplets and I/O chiplets, as well as reliable optical I/O connections.