www.power-and-beyond.com, Jul. 09, 2024 –
While the three-nanometer chip is going to witness a shortage, people on the internet are talking about the chips produced through two-nanometer and one-nanometer processes. Chip-making giants like TSMC, Intel, Samsung Semiconductors, and many more have publicly announced plans to move to two-nanometer and one-nanometer nodes in the upcoming six years. The article explains the latest news about 2-nm and 1-nm chips with their actual meaning and features.
The current transistor technology uses 7-nm, 5-nm, and 3-nm technology nodes. Looking at the transistor count history, the three-micrometer node was used in 1987. The initiation of the nanometer node happened 20 years ago through the introduction of the 90-nm process.
As of 2022, the 3-nm technology node was the smallest to be commercialized. Apple's iPhone 15 Pro and iPhone 15 Pro Max uses TSMC 3-nm chip. According to the latest buzz, the 3-nm chips are reportedly facing shortage due to high demand as all are nearly booked for the next two years.
In 2021, IBM introduced the smallest 2-nm node chip. However, such technology is in the testing phase- yet to be commercialized. All these 3-nm and 2-nm chips improve efficiency and eventually function as AI semiconductors.
Release of two-nanometer and one-nanometer chips
The chip race to achieve the smallest but efficient product has been continuing for years. The current smallest chip battle is to produce chips based on 2-nm and eventually 1-nm processes. TSMC (Taiwan Semiconductor Manufacturing Company), Intel, and Samsung have confirmed their plans to produce 2nm and 1nm chips in the coming 2-3 years. TSMC plans to commercialize 1.6-nm chips by 2026.
Similarly, Samsung is all set to launch 2-nm chips by the end of 2025 and 1.4-nm chips in 2027. Intel plans to launch 2-nm and 1.8-nm chips by 2025, and 1-nm chips by late 2027. The US Chips Act benefits these chip-makers through multi-billion dollar funds for producing smaller and better chips in their country. All chip-making giants plan to test and launch the 2nm process into 2025 and initiate mass production by 2027.
What are two-nanometer and one-nanometer chips?
In semiconductor manufacturing, the terms "process", "process node" and "technology node" are used interchangeably for 2nm, 1nm, and other nm chips. This is because all these terms represent the manufacturing process involved in chip size shrinking with a high transistor count.
In simple words, any nanometer process/technology node is a manufacturing process rather than a unit of length. The chips produced through these nanometer processes are commonly called nanometer chips. For example, the chips produced through the 2-nm process are called 2-nm chips. Similarly, chips produced through the 1-nm process are called 1-nm chips.
All the technology nodes: seven-nanometer, five-nanometer, three-nanometer, two-nanometer, and one-nanometer are marketing terms to produce smaller and more efficient ICs with high transistor count. The 5-nm process produces smaller ICs with a high transistor count compared to the 7-nm process. Similarly, a 2-nm process would produce efficient and smaller ICs with a higher transistor count than the current 3-nm process.
Is "nanometer" in the X-nm node a misnomer?
It was a common misconception that the nanometer represents the length of the gate of the transistor. The usage of "nanometers" in the 1nm process is correct because the gate length is actually in nanometers but not exactly one nanometer. The distance between the centers of two adjacent transistor gates in an IC is called gate pitch. Similarly, the distance between the centers of two adjacent metal lines in an IC metal layer is called metal pitch.
The term nanometer in the X-nm processes may point out values of gate pitch and metal pitch expressed in nanometers. The gate pitch in the 5-nm process was 51 nm and 48 nm in the 3-nm process. The metal pitch in the 5-nm process was 30 nm and 24 nm in the 3-nm process. None of the lengths were 3nm or 5nm. However, the size of the transistor is significantly reduced for lesser technology nodes.