www.cnx-software.com, Feb. 04, 2022 –
One of the main advantages of RISC-V architecture is that it is open, so any organization with the right skills can develop its own cores, and India’s government has taken up this opportunity with the Microprocessor Development Programme (MDP) helping develop VEGA RISC-V cores locally.
Thanks to funding by the Ministry of Electronics and Information Technology (MeitY), the Centre for Development of Advanced Computing (C-DAC) managed to design five RISC-V processors ranging from a single-core 32-bit RISC-V microcontroller-class processor to a Linux capable quad-core 64-bit out-of-order processor.
Key features of the five VEGA cores developed by the C-DAC:
- VEGA ET1031 – 32-bit single-core 3-stage in-order RV32IM processor with AHB/AXI4.bus, optional MMU, optional Debug
- VEGA AS1061 – 64-bit single-core 6-stage in-order RV64IMAFDC processor with 8KB D-cache, 8KB I-cache, FPU, AHB/AXI4 bus
- VEGA AS1161 – 64-bit single-core 16-stage pipeline out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, FPU, AHB/AXI4/ACE bus
- VEGA AS2161 – 64-bit dual-core 16-stage pipeline out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, 512KB L2 cache, FPU, AHB/AXI4/ACE bus
- VEGA AS4161 – 64-bit quad-core 16-stage pipeline out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, 1024KB L2 cache, FPU, AHB/AXI4/ACE bus
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