ASIC supplier GUC is supporting the leading edge 3nm N3 technology from foundry TSMC with significantly lower voltages of 0.75V.
www.eenewseurope.com, Sept. 16, 2021 –
Taiwanese ASIC comany GUC has worked with EDA vendors to build up a design flow for TSMC's N3 3nm CMOS process from RTL to GDSII. Synopsys, Cadence Design Systems and Siemens EDA are supporting the N3 process with design tools.
GUC has also completed N3 key design elements. These include a Computing Engine (CE) with 143m standard cells operating at 0.75V alongside customized low power cells for XOR, XNOR, ADDER for low power designs. A Chip Performance Monitor (CPM) helps project silicon correlation and debugging moving designs from 5nm.
GUC has also completed N3 key design elements. These include a Computing Engine (CE) with 143m standard cells operating at 0.75V alongside customized low power cells for XOR, XNOR, ADDER for low power designs. A Chip Performance Monitor (CPM) helps project silicon correlation and debugging moving designs from 5nm.
The company is now working on N3 test chips for customers and working to port its IP, including its 5nm GUC-Link 3D interconnect for chiplets announced in May, to 3nm (above).
GUC is the largest ASIC design house in the industry, with net sales for January through July 2021 of NT$7,837m (US$282m). This is up 11.4 percent compared to the same period in 2020 in the first months of the Covid-19 pandemic. Big customers with their own in-house chip designs, particularly Apple and Intel, are currently dominating TSMC's 3nm capacity.