liliputing.com, Jul. 05, 2021 –
At this year's RISC-V World Conference China, a team of more than two dozen students and professors from the Chinese Academy of Science (CAS) have unveiled the XiangShan processor that promises big performance gains over current RISC-V options.
XiangShan has been developed as an open source project with a BSD-like Mulan PSL v2 license. Since its inception in June of 2021 contributors have submitted more than 50,000 lines of code and published 400 documents.
One of the more interesting features of XiangShan is that its code is written in the Chisel hardware description language. Its creators say that resulted in a codebase that's 1/5 the size it would be if it had been written in the older Verilog language.