1 95.0

Tessent Bus Monitor The Tessent Embedded Analytics Bus Monitor provides non-intrusive monitoring of interconnect activity across all major standards, including Arm, AMBA,...

2 70.0

Unified Hardware IP for Post-Quantum Cryptography based on Kyber and Dilithium PQSecure™-CRYSTALS from PQSecure Technologies, LLC. is a set of hardware IP cores designed for various target applications of digital signatures and k...

3 53.0

Secure-IC's Securyzr Crypto Coprocessor with integrated Post-Quantum Cryptography IPs The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC....

4 51.0

TLS 1.3 - Security Protocol Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...

5 46.0

CRYSTALS-Dilithium - Post-Quantum Digital Signature IP Core Post-quantum CRYSTALS-Dilithium Digital Signature IP Core from ResQuant supports key generation, signing and signature verification operations for II,...

6 43.0

Elliptic Curve Cryptography (ECC) Accelerator The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...

7 40.0

UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8 Arasan's Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host proce...

8 40.0

Secure-IC's Securyzr(TM) Crypto Coprocessor (Compact) The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC....

9 40.0

Secure-IC's Securyzr(TM) Crypto Coprocessor (Premium) The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC....

10 40.0

Secure-IC's Securyzr(TM) Crypto Coprocessor (Standard) The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC....

11 25.0

Secure-IC's Securyzr(TM) DDR Encrypter The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory. It supports AXI slave/master interfaces,...

12 25.0

Secure-IC's Securyzr(TM) DDR Encrypter The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory. It supports AXI slave/master interfaces,...

13 20.0

Secure-IC's Securyzr™ Memory & Bus Protection IP Core The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI ...

14 11.0

CC-100IP-PI Power Integrity Enhancement IP The CC-100IP-PI on Chip IP Block is an on-chip adjustable Impedance Controlled Hyper- capacitor with a Capacitance Multiplication, Series Inductance N...

15 11.0

CC-100IP-RF Analog and RF Sensitivity Enhancement IP The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series I...

16 10.0

Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks The Synopsys ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrate security into their...

17 10.0

Post Quantum ready Public Key Crypto HW acceleration library optimized for networking applications eSi-PQC-HT is a post quantum ready Public Key Crypto HW acceleration library, optimized for networking applications. eSi-PQC-HT supports the followi...

18 8.0

CRYSTALS Kyber core for accelerating NIST FIPS 203 Key Encapsulation Mechanism eSi-Kyber is a hardware accelerator core designed to accelerate post-quantum Key Encapsulation Mechanism (KEM) as defined by NIST FIPS 203. Kyber, a...

19 7.0

TRNG IP Core TRNG IP Cores perform true random number generation in compliance with the standards and guidelines defined in 'NIST SP 800-90B'. This standard specif...

20 5.0

Attack resistant ECC hardware acceleration core eSi-ECC is a hardware acceleration core for Elliptic Curve (EC) modular arithmetic operations, which are commonly performed within EC cryptographic pr...

21 3.0

Generic Polar FEC Codec Creonic has flexible Polar decoder architecture to fulfil different customer requirements. The IP core has been demonstrated on internal conferences...

22 0.0

AES Key Wrap Crypto Accelerator The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and f...

23 0.0

AES-ECB Accelerator The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publ...

24 0.0

AES-GCM Multi-channel upto 2Tbps Crypto Accelerator The EIP-63, high speed AES-GCM engine is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES...

25 0.0

Low Power Security Engine Low Power, area-efficient, timing and side channel attack resistant security Accelerator Engine IP. Designed to meet the security requirement of resou...

26 0.0

TESIC CC EAL5+ Secure Element IP Core TESIC is a CC EAL5+ PP0084 proven/certification-ready secure element IP that is delivered as hard macro for plug-and-play System-on Chip (SoC) integra...

27 0.0

Key Expander Core The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P and AES-GCM cores. It processes 128-bit blocks, and is programmable f...

28 0.0

DPA Resistant Software Library Addressing the growing demand for readily available solutions that implement Differential Power Analysis (DPA) countermeasures, we developed a family ...

29 0.0

CryptoCell-300 - Platform Security Solution for Devices with Strict Power and Area Constraints The Arm CryptoCell-300 family of embedded security solutions serves high-efficiency systems with a small footprint and low power consumption. The Cryp...

30 0.0

Secure IP a Robust Security Enclave Kudelski IoT Secure Hardware IP has been designed for chipset manufacturers seeking key protection in their system on chip (SoC/ASIC) solutions, robus...

31 0.0

IPsec Security Processor Core implements the IPsec and SSL/TLS security standard at high data rates that require the cryptographic processing acceleration. The ISP1-128 core i...

32 0.0

Zign 100 - Software implementation of SRAM PUF The number of connected devices, machines, sensors, or simply things are linked with each other over open communication networks on the internet of th...

33 0.0

Geon Secure Execution Processor Geon Secure Execution Processor delivers secure code execution by supporting two secure contexts. All code and data belonging to a secure context is c...

34 0.0

AES Engine IP YEESTOR s AES engine (ESAES) IP is a high-performance cryptographic engine operates in AES (Rijndael) NIST Federal information processing standard FIP...